The present invention relates generally to transistor devices, and in particular to a novel inverter device and circuit structure that increases resistance at its output stage without effecting performance of the driver inverter.
Semiconductor devices that employ a first stage inverter circuit including, for example, a buffer circuit or a circuit configuration of a NAND or NOR device, are found to be increasingly susceptible to become overstressed during “burn-in” conditions, e.g., during manufacture and test.
That is, typical semiconductor device “burn in” procedures requires acceleration of failure modes by accelerated voltage and temperature conditions applied at the chip level. Under such conditions, some transistor devices such as field effect transistors (FETs) become overstressed due to device self-heating, sometimes resulting in a thermal runaway condition.
FIG. 1A shows a schematic of a conventional inverter circuit 10 comprising a N-type FET (NFET) 15 and p-type FET (PFET) 12 connected at a single driving terminal of each, e.g. a drain terminal 13, and having a common gate connection. This circuit 10 is configured as a driving stage for driving current sourced from the circuit 10 at the single common drain terminal 19 along a single conductor 18 to drive connected next stage circuitry, e.g., inverter stage 20. Further inverter circuitry 20 may be a similarly configured inverter device, however as shown, the driving input conductor 18 is split to provide two conducting paths: a first naturally resistive path 28 for driving a gate of the PFET 22 of circuit 20, and a second naturally resistive path 29 for driving a gate of the NFET 25 of circuit 20. In an implementation, the opposing FET 12, may be on the order of 10 μm-50 μm in width, and capable of supplying >10 mA current supply to opposing FET if that FET is drawing current.
Large multifingered FETs are particularly more susceptible to overstressed conditions due to both high finger density and capability of opposing FET to feed high current to the nominally off-state FET. Thus, for the prior art driving circuit 10 of FIG. 1A, under burn-in conditions, wherein the input voltage, Vg, of each gate at circuit 10 is zero (0 Volts), for example, such that NFET transistor 15 is turned off and an elevated stress voltage, VDD_stress, is applied at 16, the leakage current under VDD_stress will lead to power dissipation in the NFET 15 that is in the off-state via a low resistance supply path indicated at 19. That is, the “on” FET 12 has a low resistance, so negligible voltage drop appears across it, however, the “OFF”-state FET 15 incurs self-heating at the elevated VDD_stress voltage.
Even in an alternate configuration where Vg is applied a VDD_stress voltage thereby turning on the NFET 15, and the VDD is at the VDD_Stress voltage, the PFET device 12 will be at the elevated stress and subject to the heating via the low resistance path 19.
Thus, while a current solution such as shown in FIG. 1B may add a resistance element 24 in the low resistance path at the common terminal 13 in such circuit 10, such a solution may have higher impact on performance, or otherwise are not compatible with providing the isolation required for performance or reduced variability.
It would be highly desirable to provide a device feature and circuit configuration that lessens the susceptibility of such circuits to become overstressed in burn-in conditions, and that limit these overstress runaway outcomes, without significant impact to performance.